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M88DDR4RCD01 - Gen1 DDR4 Registering Clock Driver (RCD)

M88DDR4RCD01 is a configurable 32-bit 1:2 Registering Clock Driver (RCD) with parity for DDR4 RDIMM and LRDIMM applications. The device supports 1.2V VDD operations. The command, address and control bus inputs are pseudo-differential with an external or internal voltage reference. The outputs of these signals are full swing CMOS drivers optimized to drive single terminated 25 to 50 Ohms traces in DDR4 RDIMM and LRDIMM applications. The clock outputs Yn_t and Yn_c and control net outputs QxCKEn, QxCSn and QxODTn can be driven with a different strength to compensate for different DIMM net topologies. By disabling unused outputs the power consumption is reduced.

M88DDR4RCD01 operates from a differential clock (CK_t and CK_c). Inputs are registered at the crossing of CK_t going HIGH, and CK_c going LOW. The input signals could be either re-driven to the outputs or they could be used to access device internal control registers when certain input conditions are met.


Compliant with JEDEC DDR4RCD01 specification

Speed up to DDR4-2400

32-bit 1:2 registering buffer for address and control signals

Integrated PLL clock driver distributing one differential clock pair to five differential pairs

VDD voltage support: 1.2V

Dual and Quad chip selects support

Parity checking on command and address inputs

Output characteristics configurable through control registers

Constant propagation delay with VT variations

ZQ calibration of Ron and IBT values

Programmable latency equalization support

CA bus training mode support to align the incoming CA and CTRL signals optimally

I2C interface support

Different power saving modes such as S3 low power mode, CK Stop mode, etc.

Low power consumption

Green package: Fine-pitch Ball Grid Array (FBGA)

High-performance DDR4 RDIMM and LRDIMM

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